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Part Numbert Mfg Packt D/C Descriptiont Qty Company/Contact  
ISL6258A INTERSIL        9000 

ISL6258A Datasheet

Parameter Symbol Conditions Min Typ Max Unit
CLK pulse width WCLK 70 ns
Data setup time tSUD VIH = VDD, VIL = VSSO 50 ns
Data hold time tHD VIH = VDD, VIL = VSSO 10 ns
Latch pulse width tWLA 100 ns
Latch setup time tSULA 100 ns
CLK-SO propagation delay time tdSO CL=3 pF 120 ns
EN-DOn propagation delay time tdDO RL= 1.5 kfl, VDOH = 24 V 3.0 ,is
DOn rise time trDO RL= 1.5 kfl, VDOH = 24 V 1.0 3.0
DOn fall time tfDO RL= 1.5 kfl, VDOH = 24 V l.o 3.0
Clock frequency fCLK When cascade conneaion 5.0 MHz


ISL6258A Price
'Except for pulse detector circuitry biasing necessary for quick recovery from power down mode. "Control register buffers powered down. Data in register will not be affected but new data cannot be loaded into register when IDLEiSERVO is high.
A single capacitor on the CCFL Vc pin provides both stable loop compensation and an averaging function to the half- wave-rectified sinusoidal lamp current. Therefore, input prog ramming current relates to one-half of average lamp current. This scheme reduces the number of loop com- pensation components and permits faster loop transient response in comparison to previously published circuits. If a floating lamp configuration is used, ground the Dl0 pin.
When an external data recovery process is used with AGC, BBOUT must be coupled to the external data recovery process and CMPIN by separate series coupling capacitors. The AGC reset function is driven by the signal applied to CMPIN.